The globalization of the semiconductor supply chain brings rapid research and development (R&D) of chip fabrication and design, as well as swift adoption of the latest technology nodes. System-on-chip (SoC) has evolved in the past decades to combine different intellectual properties (IPs) into one design layout, and thus, a single die with multiple functions in one chip. However, the intensive computation workload in today's high-performance computers, data centers, cloud computing, and machine learning applications demands innovations beyond the current state-of-the-art SoC status quo. This presentation focuses on the comprehensive design, assessment, evaluation, and proposal of security assurance to ensure the trustworthiness and testability of devices. It includes a modular blockchain framework for building a tamper-resistant record for the chiplet/IC supply chain, self-referencing approaches for the detection and avoidance of counterfeit ICs, and the use of Boolean satisfiability for hardware security and VLSI testing. It also addresses the security implications and vulnerabilities for microelectronics, particularly 2.5D/3D ICs, in the coming decade, along with potential solutions.